An accurate track-and-latch comparator
نویسندگان
چکیده
منابع مشابه
A Comparative Study of Dynamic Latch Comparator
This paper presents the comparison between CMOS dynamic latch comparators. The circuit has been simulated using SPICE tool with 0.35μm technology, supply voltage of 3 V and 3.3 V respectively. The circuits studied and simulated in this paper are Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch and the Buffered dynamic latch circu...
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Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide...
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High performance analog to digital converters (ADC), memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators. This paper presents an ameliorate design for a dynamic latch based comparator in attaining high performance. The comparators accuracyis mainly defined by two fa...
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The design and analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation. Simulation results are obtained in 0.18um with supply voltages of 1....
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2012
ISSN: 1349-2543
DOI: 10.1587/elex.9.808